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july 2006 rev 2 1/23 1 m36p0r9070e0 512 mbit (x16, multiple bank, mu lti-level, burst) flash memory 128 mbit (burst) psram, 1.8v supply, multi-chip package feature summary multi-chip package ? 1 die of 512 mbit (32mb x 16, multiple bank, multi-level, burst) flash memory ?1 die of 128mbit (8mb x16) psram supply voltage ?v ddf = v ccp = v ddq = 1.7 to 1.95v ?v ppf = 9v for fast program electronic signature ? manufacturer code: 20h ? device code: 8819 ecopack? package available flash memory synchronous / asynchronous read ? synchronous burst read mode: 108mhz, 66mhz ? asynchronous page read mode ? random access: 96ns programming time ? 4.2s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 64 mbit banks ? four extended flash array (efa) blocks of 64 kbits dual operations ? program/erase in one bank while read in others ? no delay between read and write operations security ? 2112-bit user programmable otp cells ? 64-bit unique device number 100,000 program/erase cycles per block common flash interface (cfi) block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp f for block lock-down ? absolute write protection with v ppf = v ss psram access time: 70ns user-selectable operating modes ? asynchronous modes: random read, and write, page read ? synchronous modes: nor-flash, full synchronous (burst read and write) asynchronous page read ? page size: 4, 8 or 16 words ? subsequent read within page: 20ns burst read ? fixed length (4, 8, 16 or 32 words) or continuous ? maximum clock frequency: 80mhz low power consumption ? active current: < 25ma ? standby current: 200a ? deep power-down current: 10a low power features ? partial array self refresh (pasr) ? deep power-down (dpd) mode tfbga107 (zac) fbga www.st.com
contents m36p0r9070e0 2/23 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 flash chip enable input (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 flash output enable inputs (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 flash write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 flash write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 flash reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 psram chip enable input (e p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 psram configuration register enable (cr p ) . . . . . . . . . . . . . . . . . . . . . 11 2.17 deep power-down input (dpd f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.18 v ddf supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.19 v ccp supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.20 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 v ppf program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.22 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m36p0r9070e0 contents 3/23 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
list of tables m36p0r9070e0 4/23 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
m36p0r9070e0 list of figures 5/23 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. tfbga107 8 11mm - 9 12 active ball array, 0.8mm pitch, package outline. . . . . . . . . 19
summary description m36p0r9070e0 6/23 1 summary description the m36p0r9070e0 combines two memory devices in one multi-chip package: 512-mbit multiple bank flash memory (the m58pr512j). 128 mbit psram (the m69kb128ab). the purpose of this document is to describe how the two memory components operate with respect to each other. it should be read in conjunction with the m58prxxxj and m69kb128ab datasheets, where all specifications required to operate the flash memory and psram components are fully detailed. the m58pr512j and m69kb128ab datasheets are available from www.st.com . recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga107 package. it is supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai10845 25 a0-a24 e f dq0-dq15 v ddq m36p0r9070e0 g f v ss 16 w f rp f wp f v ddf dpd f e p g p w p ub p lb p v ppf v ccp l k cr p wait
m36p0r9070e0 summary description 7/23 table 1. signal names a0-a24 (1) 1. a23-a24 are address inputs for the flash memory component only. address inputs dq0-dq15 common data input/output v ddq common flash and psram power supply for i/o buffers v ppf flash memory optional supply voltage for fast program & erase v ddf flash memory power supply v ccp psram power supply v ss ground l latch enable input k burst clock wait wait output nc not connected internally du do not use as internally connected flash memory e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input dpd f deep power-down psram e p chip enable input g p output enable input w p write enable input cr p configuration register enable input ub p upper byte enable input lb p lower byte enable input
summary description m36p0r9070e0 8/23 figure 2. tfbga connections (top view through package) ai11098b nc dq14 dq0 a16 wait dq13 dq8 h dq7 d c a17 a22 b a21 a 8 7 6 5 4 3 2 1 a5 a3 g f e a1 du k a7 a2 a8 du a11 w p a13 du 9 a4 a12 m l k j dq15 v ss nc du nc dq6 nc du dq12 l nc dq4 dq10 v ss v pp a18 v ss dq11 dq1 a23 a24 nc a19 nc du dq9 a14 nc a20 v ddf dq3 dq5 dq2 a6 du du du du nc nc du nc nc nc v ccp dpd f v ss nc v ss nc v ss v ss v ddq v ddq du du du lb p e p a9 wp f a10 a15 ub p rp f w f g p a0 nc e f g f v ccp v ddq cr p v ss v ddq v ddf v ss v ss v ss v ss
m36p0r9070e0 signal descriptions 9/23 2 signal descriptions see figure 1., logic diagram and table 1., signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a24) addresses a0-a22 are common inputs for the flash memory and psram components. addresses a23 and a24 are inputs for flash memory components only. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the internal state machine. the flash memory is accessed through the chip enable signal (e f ) and through the write enable signal (w f ), while the psram is accessed through the chip enable signal (e p ) and the write enable signal (w p ). e f low, and e p must not be low at the same time. 2.2 data input/output (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. for the psram component, the upper byte data inputs/outputs (dq8-dq15) carry the data to or from the upper part of the selected address when upper byte enable (ub p ) is driven low. the lower byte data inputs/outputs (dq0-dq7) carry the data to or from the lower part of the selected address when lower byte enable (lb p ) is driven low. when both ub p and lb p are disabled, the data inputs/ outputs are high impedance. 2.3 latch enable (l ) the latch enable pin is common to the flash memory and psram components. for details of how the latch enable signal behaves, please refer to the datasheets of the respective memory components: m69kb128ab for the psram and m58pr512j for the flash memory. 2.4 clock (k) the clock input pin is common to the flash memory and psram components. for details of how the clock signal behaves, please refer to the datasheets of the respective memory components: m69kb128ab for the psram and m58pr512j for the flash memory.
signal descriptions m36p0r9070e0 10/23 2.5 wait (wait) wait is an output pin common to the flash memory and psram components. however the wait signal does not behave in the same way for the psram and the flash memory. for details of how it behaves, please refer to the m69kb128ab datasheet for the psram and to the m58pr512j datasheet for the flash memory. 2.6 flash chip enable input (e f ) the flash chip enable input activates the control logic, input buffers, decoders and sense amplifiers of the flash memory component selected. when chip enable is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the corresponding flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to have e f at v il and e p at v il at the same time. only one memory component can be enabled at a time. 2.7 flash output enable inputs (g f ) the output enable pins control the data outputs during flash memory bus read operations. 2.8 flash write enable (w f ) the write enable controls the bus write operation of the flash memory command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. 2.9 flash write protect (wp f ) write protect is an input that gives an additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (see the lock status table in the m58pr512j datasheet).
m36p0r9070e0 signal descriptions 11/23 2.10 flash reset (rp f ) the reset input provides a hardware reset of the flash memories. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to the m58prxxxj datasheet, for the value of i dd2 . after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to the m58prxxxj datasheet). 2.11 psram chip enable input (e p ) the chip enable input activates the psram when driven low (asserted). when deasserted (v ih ), the device is disabled, and goes automatically in low-power standby mode or deep power-down mode. 2.12 psram write enable (w p ) write enable, w p , controls the bus write operation of the psram. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.13 psram output enable (g p ) o utput enable, g p , provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. 2.14 psram upper byte enable (ub p ) the upper byte en-able, ub p , gates the data on the upper byte data inputs/outputs (dq8- dq15) to or from the upper part of the selected address during a write or read operation. 2.15 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte data inputs/outputs (dq0- dq7) to or from the lower part of the selected address during a write or read operation. if both lb p and ub p are disabled (high) during an operat ion, the device will disable the data bus from receiving or transmitting data. alth ough the device will seem to be deselected, it remains in an active mode as long as e p remains low. 2.16 psram configuration register enable (cr p ) when this signal is driven high, v ih , write operations load either the value of the refresh configuration register (rcr) or the bus configuration register (bcr).
signal descriptions m36p0r9070e0 12/23 2.17 deep power-down input (dpd f ) the deep power-down input is used to place the device in a deep power-down mode.when the device is in deep power-down mode, the memory cannot be modified and data is protected. for further details on how the deep power-down input signal works, please refer to the m58pr512j datasheet. 2.18 v ddf supply voltages v ddf provides the power supply to the internal cores of the flash memory. it is the main power supply for all flash memory operations (read, program and erase). 2.19 v ccp supply voltage v ccp provides the power supply to the internal core of the psram device. it is the main power supply for all psram operations. 2.20 v ddq supply voltage v ddq provides the power supply for the flash me mory and psram i/o pins. this allows all outputs to be powered independently of the flash memory and sram core power supplies, v ddf and v ccp . 2.21 v ppf program supply voltage v ppf is both a control input and a power supply pin for the flash memory. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddq ) v ppf is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v ppf > v pp1 enables these functions (see the m58prxxxj datasheet for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed.
m36p0r9070e0 signal descriptions 13/23 2.22 v ss ground v ss is the common ground reference for all voltage measurements in the flash (core and i/o buffers) and psram chips. it must be connected to the system ground. note: each flash memory device in a system should have their supply voltage (v ddf ) and the program supply voltage v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capaci tors should be as close as possible to the package). see figure 5., ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents .
functional description m36p0r9070e0 14/23 3 functional description the psram and flash memory components have separate power supplies but share the same grounds. they are distinguished by two chip enable inputs: e f for flash and e p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is a simultaneous read operations on the flash memory and the psram which would result in a data bus contention. therefore it is recommended to put the other devices in the high impedance state when reading the selected device. figure 3. functional block diagram ai11731 e p cr p g p w p a0-a22 128mbit psram ub p lb p wait k v ddq v ss v ccp l 512 mbit flash memory e f g f v ddf w f rp f wp f v ppf a23-a24 dq0-dq15 dpd f
m36p0r9070e0 functional description 15/23 table 2. main operating modes (1) operation e f g f w f rp f dpd f (2) wait (3) l e p w p g p ub p lb p cr p a19 a18 a0- a17 a20- a22 dq0- dq7 dq8- dq15 flash memory bus read v il v il v ih v ih de-a (4) v il (5) psram must be disabled data output bus write v il v ih v il v ih de-a (4) v il (5) data input address latch v il xv ih v ih de-a (4) v il data output or hi-z (6) output disable v il v ih v ih v ih de-a (4) hi-z x any psram mode is allowed hi-z standby v ih xxv ih de-a (4) hi-z x hi-z reset x x x v il de-a (4) hi-z x hi-z deep power- down v ih xxv ih a (7) hi-z x hi-z psram word read the flash memory must be disabled low- z v il v il v ih v il v il v il v il valid output valid output valid lower byte read v il v ih v il v il valid output valid high-z upper byte read v il v il v ih v il valid high-z output valid word write v il xv il v il v il valid input valid input valid lower byte write xv ih v il v il valid input valid invalid upper byte write xv il v ih v il valid invalid input valid read cr (cr controlled method) v ih v il v il v il v ih 00(rcr)1 0(bcr)x1 (didr) (8) x bcr/rcr/ didr content program cr (cr controlled) (9) v ih xx x 00(rcr) 10(bcr) (8) bcr/ rcr data high-z no operation any flash memory mode is allowed x xx x x v il xx x x deep power- down (10) hi-z v ih x x x x x x x x high-z standby v ih xx x x v il x x x high-z 1. x = don't care, de-a = de-asserted, a = asserted, cr = configuration register. 2. the dpd f signal polarity depends on the value of the ecr14 bit. 3. in the flash memory the wait signal polarity is configured using the set configuration register command. 4. if ecr15 is set to '0', the flash memory cannot enter the deep power-down mode, even if dpd f is asserted. 5. in the flash memory l can be tied to v ih if the valid address has been previously latched. 6. depends on g f . 7. ecr15 has to be set to ?1? for the flash memory to enter deep power-down. 8. a18 and a19 are used to select the bcr, rcr or didr registers. 9. bcr and rcr only. 10. bit 4 of the refresh configuration register must be set to ?0?, bit 4 (bcr4) of the bus configuration register must be set t o ?0?, and e has to be maintained high, v ih , during deep power-down mode.
maximum rating m36p0r9070e0 16/23 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?30 85 c t bias temperature under bias ?30 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.2 2.45 v v dd supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 2.45 v v pp program voltage ?1.0 11.5 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m36p0r9070e0 dc and ac parameters 17/23 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter flash memory psram unit min max min max v ccp supply voltage ??1.71.95v v ddf supply voltage 1.7 1.95 ? ? v v ddq supply voltage 1.7 1.95 1.7 1.95 v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ? ? v ambient operating temperature ?30 85 ?30 85 c load capacitance (c l )3030pf impedance output (z 0 )50 ? output circuit protection resistance (r) 50 ? input rise and fall times 3 2 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
dc and ac parameters m36p0r9070e0 18/23 figure 5. ac measurement load circuit please refer to the m58prxxxj and m69kb 128ab datasheets for further dc and ac characteristic values and illustrations. table 5. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 14 pf c out output capacitance v out = 0v 14 pf ai06162a v ccq /2 c l r device under test z 0 out
m36p0r9070e0 package mechanical 19/23 6 package mechanical in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 6. tfbga107 8 11mm - 9 12 active ball array, 0.8mm pitch, package outline 1. drawing is not to scale. e d eb se a2 a1 a bga-z85 ddd fd d1 e1 e fe ball "b1"
package mechanical m36p0r9070e0 20/23 table 6. stacked tfbga107 8 11mm - 9 12 active ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.20 0.008 a2 0.85 0.033 b 0.35 0.30 0.40 0.014 0.012 0.016 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 6.40 0.252 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 8.80 0.346 e0.80 0.031 fd 0.80 0.031 fe 1.10 0.043 se 0.40 0.016
m36p0r9070e0 part numbering 21/23 7 part numbering note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. table 7. ordering information scheme m36p0r9070e 0zace example: device type m36 = multi-chip package (multiple flash + psram) flash 1 architecture p = multi-level, multiple bank, large buffer flash 2 architecture 0 = no die operating voltage r = v ddf = v ccp = v ddq = 1.7 to 1.95v flash 1 density 9 = 512 mbits flash 2 density 0 = no die ram 1 density 7 = 128 mbits ram 0 density 0 = no die parameter blocks location e = even block flash memory configuration product version 0 = 90nm flash technology, 96ns speed; psram package zac= stacked tfbga107 c stacked footprint. option blank = standard packing e = ecopack? package, standard packing f = ecopack? package, tape & reel packing
revision history m36p0r9070e0 22/23 8 revision history table 8. document revision history date revision changes 28-nov-2005 1 initial release. 13-jul-2006 2 document status promoted from preliminary data to full datasheet. document updated to latest version of m58prxxxj datasheet, dc characteristics tables removed (f or values refer to m58prxxxj and m69kb128ab datasheets). psram part replaced by m69kb128ab. h9 ball is du in figure 2: tfbga connections (top view through package) . t stg min and v pp max modified in table 3: absolute maximum ratings . table 2: main operating modes modified. psram value for input rise and fall times filled in in ta bl e 4 : operating and ac measurement conditions .
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